1. Field of the Invention
The present invention relates generally to a semiconductor device. More specifically, the present invention relates to a dual-channel transistor for ultra-high density semiconductor devices including a dynamic random access memory (DRAM) and a fabrication method thereof.
2. Description of the Prior Art
As known in the art, DRAM is a combination of a large number of DRAM cells. A metal oxide semiconductor (MOS) transistor and a capacitor connected in series constitute a DRAM cell. The MOS transistor is a switch device for controlling the data input or output from the capacitor.
The design of the capacitor of the DRAM cell involves two conductive layers and an insulating layer. The two conductive layers act as the upper and lower electrodes, respectively, and the insulating layer separates the two electrodes. When a predetermined voltage is applied between the two electrodes, charges are stored in the insulating layer disposed between the two electrodes. With advance of semiconductor processing technology, the volume and the unit size of the DRAM cell continue to shrink in an aggressive manner.
With the continuing shrinkage of device feature size, it becomes increasingly difficult to overcome the short channel effect (SCE) as the gate channel length of a memory cell transistor becomes shortened. The SCE due to shrunk gate channel length can hinder further integration of the IC chips. Many efforts have been made for solving this problem, for example, by reducing the thickness of the gate dielectric layer or by increasing the doping concentration of the source/drain region. However, these approaches are impracticable because they tend to adversely affect the device reliability and degrade speed of data transfer.
Another problem includes an increased junction leakage current. As the junction leakage current increases, the data retention time is reduced and the refresh characteristic of the memory device is deteriorated. The contact area of a contact plug that contacts with a source/drain region is also reduced. Thus, the electrical resistance of the contact plug is increased and this becomes an obstacle to the stable and steady operation of the memory device.
It is also highly desirable to put as many memory cells as possible in a single wafer. To maximize the memory cell packing density, the cell area of each unit memory cell has to be minimized.